Going Deeper#

This section will talk about more advanced SKiDL features that make designing complicated circuits easier.

Basic SKiDL Objects#

SKiDL uses four types of objects to represent a circuit: Part, Pin, Net, and Bus.

The Part object represents an electronic component, which SKiDL thinks of as a simple bag of Pin objects with a few other attributes attached (like the part number, name, reference, value, footprint, etc.).

The Pin object represents a terminal that brings an electronic signal into and out of the part. Each Pin object store information on which part it belongs to and which nets it is attached to.

A Net object is kind of like a Part: it’s a simple bag of pins. But unlike a part, pins can be added to a net when a pin on some part is attached or when it is merged with another net.

Finally, a Bus is just a collection of multiple Net objects. A bus of a certain width can be created from a number of existing nets, newly-created nets, or both.

Creating SKiDL Objects#

Here’s the most common way to create a part in your circuit:

my_part = Part('some_library', 'some_part_name')

When this is processed, the current directory will be checked for a file called some_library.lib or some_library.kicad_sym which will be opened and scanned for a part with the name some_part_name. If the file is not found or it doesn’t contain the requested part, then the process will be repeated using KiCad’s default library directory. (You can change SKiDL’s library search by changing the list of directories stored in the skidl.lib_search_paths_kicad list.)

You’re not restricted to using only the current directory or the KiCad default directory to search for parts. You can also search any file for a part by using a full file name:

my_part = Part('C:/my_libs/my_great_parts.lib', 'my_super_regulator')

You’re also not restricted to getting an exact match on the part name: you can use a regular expression instead. For example, this will find a part with “358” anywhere in a part name or alias:

my_part = Part('Amplifier_Audio', '.*386.*')

If the regular expression matches more than one part, then you’ll only get the first match and a warning that multiple parts were found.

Once you have the part, you can set its attributes as was described previously.

Creating nets and buses is straightforward:

my_net = Net()               # An unnamed net.
my_other_net = Net('Fred')   # A named net.
my_bus = Bus('bus_name', 8)  # Named, byte-wide bus with nets bus_name0, bus_name1, ...
anon_bus = Bus(4)            # Four-bit bus with an automatically-assigned name.

As with parts, SKiDL will alter the name you assign if it collides with another net or bus having the same name.

You can also create a bus by combining existing nets, buses, or the pins of parts in any combination:

my_part = Part('Amplifier_Audio', 'LM386')
a_net = Net()
b_net = Net()
bus_nets = Bus('net_bus', a_net, b_net)            # A 2-bit bus from nets.
bus_pins = Bus('pin_bus', my_part[1], my_part[3])  # A 2-bit bus from pins.
bus_buses = Bus('bus_bus', my_bus)                 # An 8-bit bus.
bus_combo = Bus('mongrel', 8, a_net, my_bus, my_part[2])  # 8+1+8+1 = 18-bit bus.

You can also build a bus incrementally by inserting or extending it with widths, nets, buses or pins:

bus = Bus('A', 8)   # Eight-bit bus.
bus.insert(4, Bus('I', 3))  # Insert 3-bit bus before bus line bus[4].
bus.extend(5, Pin(), Net()) # Extend bus with another 5-bit bus, a pin, and a net.

And finally, you can create a Pin object although you’ll probably never do this unless you’re building a Part object from scratch:

>>> p = Pin(num=1, name='my_pin', func=Pin.TRISTATE)
>>> p
Pin ???/1/my_pin/TRISTATE

Finding SKiDL Objects#

If you want to access a bus, net, or part that’s already been created, use the get() class method:

n = Net.get('Fred')  # Find the existing Net object named 'Fred'.
b = Bus.get('A')     # Find the existing Bus object named 'A'.
p = Part.get('AS6C1616')  # Find all parts with this part name.

If a net or bus with the exact name is found (no wild-card searches using regular expressions are allowed), then that SKiDL object is returned. Otherwise, None is returned.

For parts, the search is performed using string matching on part names, references (e.g., R4), and aliases. In addition, regular expression matching is used to search within the part descriptions, so you could search for all parts with “ram” in their description.

If you want to access a particular bus or net and create it if it doesn’t already exist, then use the fetch() class method:

n = Net.fetch('Fred')  # Find the existing Net object named 'Fred' or create it if not found.
b = Bus.fetch('A', 8)  # Find the existing Bus object named 'A' or create it if not found.

Note that with the Bus.fetch() method, you also have to provide the arguments to build the bus (such as its width) in case it doesn’t exist.

Copying SKiDL Objects#

Instead of creating a SKiDL object from scratch, sometimes it’s easier to just copy an existing object. Here are some examples of creating a resistor and then making some copies of it:

>>> r1 = Part('Device', 'R', value=500)    # Add a resistor to the circuit.
>>> r2 = r1.copy()                         # Make a single copy of the resistor.
>>> r2_lst = r1.copy(1)                    # Make a single copy, but return it in a list.
>>> r3 = r1.copy(value='1K')               # Make a single copy, but give it a different value.
>>> r4 = r1(value='1K')                    # You can also call the object directly to make copies.
>>> r5, r6, r7 = r1(3, value='1K')         # Make three copies of a 1-KOhm resistor.
>>> r8, r9, r10 = r1(value=[110,220,330])  # Make three copies, each with a different value.
>>> r11, r12 = 2 * r1                      # Make copies using the '*' operator.
>>> r13, r14 = 2 * r1(value='1K')          # This actually makes three 1-KOhm resistors!!!

The last example demonstrates an unexpected result when using the * operator:

The resistor is called with a value of 1-KOhm, creating a copy of the resistor with that value of resistance.
The * operator is applied to the resistor copy, returning two more 1-KOhm resistors. Now the original resistor has been copied three times.
The two new resistors returned by the * operator are assigned to r13 and r14.

After these operations, the second and third copies can be referenced, but any reference to the first copy has been lost so it just floats around, unconnected to anything, only to raise errors later when the ERC is run.

In some cases it’s clearer to create parts by copying a template part that doesn’t actually get included in the netlist for the circuitry:

>>> rt = Part('Device', 'R', dest=TEMPLATE)  # Create a resistor just for copying. It's not added to the circuit.
>>> r1, r2, r3 = rt(3, value='1K')           # Make three 1-KOhm copies that become part of the actual circuitry.

Accessing Part Pins#

You can access the pins on a part or the individual nets of a bus using numbers, slices, strings, and regular expressions, either singly or in any combination.

Suppose you have a PIC10 processor in a six-pin package:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> pic10

 PIC10F220-IOT (PIC10F222-IOT): 512W Flash, 24B SRAM, SOT-23-6
    Pin U3/1/GP0/BIDIRECTIONAL
    Pin U3/2/VSS/POWER-IN
    Pin U3/3/GP1/BIDIRECTIONAL
    Pin U3/4/GP2/BIDIRECTIONAL
    Pin U3/5/VDD/POWER-IN
    Pin U3/6/GP3/INPUT

The most natural way to access one of its pins is to give the pin number in brackets:

>>> pic10[3]
Pin U1/3/GP1/BIDIRECTIONAL

(If you have a part in a BGA package with pins numbers like C11, then you’ll have to enter the pin number as a quoted string like ‘C11’.)

You can also get several pins at once in a list:

>>> pic10[3,1,6]
[Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/6/GP3/INPUT]

You can even use Python slice notation:

>>> pic10[2:4]  # Get pins 2 through 4.
[Pin U1/2/VSS/POWER-IN, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]
>>> pic10[4:2]  # Get pins 4 through 2.
[Pin U1/4/GP2/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN]
>>> pic10[:]    # Get all the pins.
[Pin U1/1/GP0/BIDIRECTIONAL,
 Pin U1/2/VSS/POWER-IN,
 Pin U1/3/GP1/BIDIRECTIONAL,
 Pin U1/4/GP2/BIDIRECTIONAL,
 Pin U1/5/VDD/POWER-IN,
 Pin U1/6/GP3/INPUT]

(It’s important to note that the slice notation used by SKiDL for parts is slightly different than standard Python. In Python, a slice n:m would fetch indices n, n+1, …, m-1. With SKiDL, it actually fetches all the way up to the last number: n, n+1, …, m-1, m. The reason for doing this is that most electronics designers are used to the bounds on a slice including both endpoints. Perhaps it is a mistake to do it this way. We’ll see…)

In addition to the bracket notation, you can also get a single pin using an attribute name that begins with a ‘p’ followed by the pin number:

>>> pic10.p2
Pin U1/2/VSS/POWER-IN

Instead of pin numbers, sometimes it makes the design intent more clear to access pins by their names. For example, it’s more obvious that a voltage supply net is being attached to the power pin of the processor when it’s expressed like this:

pic10['VDD'] += Net('supply_5V')

Like pin numbers, pin names can also be used as attributes to access the pin:

>>> pic10.VDD
Pin U1/5/VDD/POWER-IN

You can use multiple names to get more than one pin:

>>> pic10['VDD','VSS']
[Pin U1/5/VDD/POWER-IN, Pin U1/2/VSS/POWER-IN]

It can be tedious and error prone entering all the quote marks if you’re accessing many pin names. SKiDL lets you enter a single, comma or space-delimited string of pin names:

>>> pic10['GP0 GP1 GP2']
[Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]

Some parts have sequentially-numbered sets of pins like the address and data buses of a RAM. SKiDL lets you access these pins using a slice-like notation in a string like so:

>>> ram = Part('Memory_RAM', 'AS6C1616')
>>> ram['DQ[0:2]']
[Pin U2/29/DQ0/BIDIRECTIONAL, Pin U2/31/DQ1/BIDIRECTIONAL, Pin U2/33/DQ2/BIDIRECTIONAL]

Or you can access the pins in the reverse order:

>>> ram = Part('memory', 'sram_512ko')
>>> ram['DQ[2:0]']
[Pin U2/33/DQ2/BIDIRECTIONAL, Pin U2/31/DQ1/BIDIRECTIONAL, Pin U2/29/DQ0/BIDIRECTIONAL]

Some parts (like microcontrollers) have long pin names that list every function a pin supports (e.g. GP1/AN1/ICSPCLK). Employing the complete pin name is tedious to enter correctly and obfuscates which particular function is being used. SKiDL offers two ways to deal with this: 1) split the pin names into a set of shorter aliases, or 2) match pin names using regular expressions.

If a part has pin names where the subnames are separated by delimiters such as /, then the subnames for each pin can be assigned as aliases:

>>> pic10[3].name = 'GP1/AN1/ICSPCLK'  # Give pin 3 a long name.
>>> pic10[3].split_name('/')           # Split pin 3 name into aliases.
>>> pic10.split_pin_names('/')         # Split all pin names into aliases.
>>> pic10[3].aliases                   # Show aliases for pin 3.
{'AN1', 'GP1', 'ICSPCLK'}
>>> pic10['AN1'] += Net('analog1')     # Connect a net using the pin alias.
>>> pic10.AN1 += Net('analog2')        # Or access the alias thru an attribute.

You can also split the pin names when you create the part:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot', pin_splitters='/')

The other way to access a pin with a long name is to use a regular expression. You’ll have to enable regular expression matching for a particular part (it’s off by default), and you’ll have to use an odd-looking expression, but here’s how it’s done:

>>> pic10[3].name = 'GP1/AN1/ICSPCLK'
>>> pic10.match_pin_regex = True          # Enable regular expression matching.
>>> pic10['.*\/AN1\/.*] += Net('analog1)  # I told you the expression was strange!

Since you can access pins by number or by name using strings or regular expressions, it’s worth discussing how SKiDL decides which one to select. When given a pin index, SKiDL stops searching and returns the matching pins as soon as one of the following conditions succeeds:

One or more pin numbers match the index.
One or more pin aliases match the index using standard string matching.
One or more pin names match the index using standard string matching.
One or more pin aliases match the index using regular expression matching.
One or more pin names match the index using regular expression matching.

Since SKiDL prioritizes pin number matches over name matches, what happens when you use a name that is the same as the number of another pin? For example, a memory chip in a BGA would have pin numbers A1, A2, A3, … but might also have address pins named A1, A2, A3, … . In order to specifically target either pin numbers or names, SKiDL provides the p and n part attributes:

ram['A1, A2, A3']    # Selects pin numbers A1, A2 and A3 if the part is a BGA.
ram.p['A1, A2, A3']  # Use the p attribute to specifically select pin numbers A1, A2 and A3.
ram.n['A1, A2, A3']  # Use the n attribute to specifically select pin names A1, A2 and A3.

Part objects also provide the get_pins() function which can select pins in even more ways. For example, this would get every bidirectional pin of the processor:

>>> pic10.get_pins(func=Pin.BIDIR)
[Pin U1/1/GP0/BIDIRECTIONAL, Pin U1/3/GP1/BIDIRECTIONAL, Pin U1/4/GP2/BIDIRECTIONAL]

You can access part pins algorithmically in a loop like this:

for p in pic10.get_pins():
  <do something with p>

Or do the same thing using a Part object as an iterator:

for p in pic10:
  <do something with p>

Accessing Bus Lines#

Accessing the individual lines of a bus works similarly to accessing part pins:

>>> a = Net('NET_A')  # Create a named net.
>>> b = Bus('BUS_B', 4, a)  # Create a five-bit bus.
>>> b
BUS_B:
        BUS_B0:  # Note how the individual lines of the bus are named.
        BUS_B1:
        BUS_B2:
        BUS_B3:
        NET_A:   # The last net retains its original name.

>>> b[0]  # Get the first line of the bus.
BUS_B0:

>>> b[2,4]  # Get the second and fourth bus lines.
[BUS_B2: , NET_A: ]

>>> b[3:0]  # Get the first four bus lines in reverse order.
[BUS_B3: , BUS_B2: , BUS_B1: , BUS_B0: ]

>>> b[-1]  # Get the last bus line.
NET_A: 

>>> b['BUS_B.*']  # Get all the bus lines except the last one.
[BUS_B0: , BUS_B1: , BUS_B2: , BUS_B3: ]

>>> b['NET_A']  # Get the last bus line.
NET_A:

>>> for line in b:  # Access lines in bus using bus as an iterator.
...:    print(line)
...:
BUS_B0:
BUS_B1:
BUS_B2:
BUS_B3:
NET_A:

Making Connections#

Pins, nets, parts and buses can all be connected together in various ways, but the primary rule of SKiDL connections is:

Note

The += operator is the only way to make connections!

At times you’ll mistakenly try to make connections using the assignment operator (=). In many cases, SKiDL warns you if you do that, but there are situations where it can’t (because Python is a general-purpose programming language where assignment is a necessary operation). So remember the primary rule!

After the primary rule, the next thing to remember is that SKiDL’s main purpose is creating netlists. To that end, it handles four basic, connection operations:

Net-to-Net: Connecting one net to another merges the pins on both nets into a single, larger net.
Pin-to-Net: A pin is connected to a net, adding it to the list of pins connected to that net. If the pin is already attached to other nets, then those nets are merged with this net.
Net-to-Pin: This is the same as doing a pin-to-net connection.
Pin-to-Pin: A net is created and both pins are attached to it. If one or both pins are already connected to other nets, then those nets are merged with the newly-created.

For each type of connection operation, there are three variants based on the number of things being connected:

One-to-One: This is the most frequent type of connection, for example, connecting one pin to another or connecting a pin to a net.
One-to-Many: This mainly occurs when multiple pins are connected to the same net, like when multiple ground pins of a chip are connected to the circuit ground net.
Many-to-Many: This usually involves bus connections to a part, such as connecting a bus to the data or address pins of a processor. For this variant, there must be the same number of things to connect in each set, e.g. you can’t connect three pins to four nets.

As a first example, let’s connect a net to a pin on a part:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')  # Get a part.
>>> io = Net('IO_NET')  # Create a net.
>>> pic10.GP0] += io    # Connect the net to a part pin.
>>> io                  # Show the pins connected to the net.
IO_NET: Pin U5/1/GP0/BIDIRECTIONAL

You can do the same operation in reverse by connecting the part pin to the net with the same result:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> io = Net('IO_NET')
>>> io += pic10*GP0     # Connect a part pin to the net.
>>> io
IO_NET_1: Pin U6/1/GP0/BIDIRECTIONAL

You can also connect a pin directly to another pin. In this case, an implicit net will be created between the pins that you can access using the net attribute of either part pin:

>>> pic10.GP1 += pic10.GP2  # Connect two pins together.
>>> pic10.GP1.net           # Show the net connected to the pin.
N$1: Pin U6/3/GP1/BIDIRECTIONAL, Pin U6/4/GP2/BIDIRECTIONAL
>>> pic10.GP2.net           # Show the net connected to the other pin. Same thing!
N$1: Pin U6/3/GP1/BIDIRECTIONAL, Pin U6/4/GP2/BIDIRECTIONAL

You can connect multiple pins, all at once:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') 
>>> pic10[1] += pic10[2,3,6]
>>> pic10[1].net
N$1: Pin U7/1/GP0/BIDIRECTIONAL, Pin U7/2/VSS/POWER-IN, Pin U7/3/GP1/BIDIRECTIONAL, Pin U7/6/GP3/INPUT

Or you can do it incrementally:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') 
>>> pic10[1] += pic10[2]
>>> pic10[1] += pic10[3]
>>> pic10[1] += pic10[6]
>>> pic10[1].net
N$1: Pin U8/1/GP0/BIDIRECTIONAL, Pin U8/2/VSS/POWER-IN, Pin U8/3/GP1/BIDIRECTIONAL, Pin U8/6/GP3/INPUT

If you connect pins on separate nets together, then all the pins are merged onto the same net:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') 
>>> pic10[1] += pic10[2]  # Put pins 1 & 2 on one net.
>>> pic10[3] += pic10[4]  # Put pins 3 & 4 on another net.
>>> pic10[1] += pic10[4]  # Connect two pins from different nets.
>>> pic10[3].net          # Now all the pins are on the same net!
N$9: Pin U9/1/GP0/BIDIRECTIONAL, Pin U9/2/VSS/POWER-IN, Pin U9/3/GP1/BIDIRECTIONAL, Pin U9/4/GP2/BIDIRECTIONAL

Here’s an example of connecting a three-bit bus to three pins on a part:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') 
>>> b = Bus('GP', 3)                # Create a 3-bit bus.
>>> pic10['GP2 GP1 GP0'] += b[2:0]  # Connect bus to part pins, one-to-one.
>>> b
GP:
        GP0: Pin U10/1/GP0/BIDIRECTIONAL
        GP1: Pin U10/3/GP1/BIDIRECTIONAL
        GP2: Pin U10/4/GP2/BIDIRECTIONAL

But SKiDL will warn you if there aren’t the same number of things to connect on each side:

>>> pic10[4,3,1] += b[1:0]  # Too few bus lines for the pins!
ERROR: Connection mismatch 3 != 2!
---------------------------------------------------------------------------
ValueError                                Traceback (most recent call last)
<ipython-input-83-48a1e46383fe> in <module>
----> 1 pic10[4,3,1] += b[1:0]

/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/netpinlist.py in __iadd__(self, *nets_pins_buses)
     60         if len(nets_pins) != len(self):
     61             if Net in [type(item) for item in self] or len(nets_pins) > 1:
---> 62                 log_and_raise(
     63                     logger,
     64                     ValueError,

/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/utilities.py in log_and_raise(logger_in, exc_class, message)
    785 def log_and_raise(logger_in, exc_class, message):
    786     logger_in.error(message)
--> 787     raise exc_class(message)
    788 
    789 

ValueError: Connection mismatch 3 != 2!

Making Serial, Parallel, and Tee Networks#

The previous section showed some general-purpose techniques for connecting parts, but SKiDL also has some specialized syntax for wiring two-pin components in parallel or serial. For example, here is a network of four resistors connected in series between power and ground:

vcc, gnd = Net('VCC'), Net('GND')
r1, r2, r3, r4 = Part('Device', 'R', dest=TEMPLATE) * 4
ser_ntwk = vcc & r1 & r2 & r3 & r4 & gnd

It’s also possible to connect the resistors in parallel between power and ground:

par_ntwk = vcc & (r1 | r2 | r3 | r4) & gnd

Or you can do something like placing pairs of resistors in series and then paralleling those combinations like this:

combo_ntwk = vcc & ((r1 & r2) | (r3 & r4)) & gnd

The examples above work with non-polarized components, but what about parts like diodes? In that case, you have to specify the pins explicitly with the first pin connected to the preceding part and the second pin to the following part:

d1 = Part('Device', 'D')
polar_ntwk = vcc & r1 & d1['A,K'] & gnd  # Diode anode connected to resistor and cathode to ground.

Explicitly listing the pins also lets you use multi-pin parts with networks. For example, here’s an NPN-transistor amplifier:

q1 = Part('Device', 'Q_NPN_ECB')
ntwk_ce = vcc & r1 & q1['C,E'] & gnd  # VCC through load resistor to collector and emitter attached to ground.
ntwk_b = r2 & q1['B']  # Resistor attached to base.

That’s all well and good, but how do you connect to internal points in these networks where the interesting things are happening? For instance, how do you apply an input to the transistor circuit and then connect to the output? One way is by inserting nets inside the network:

inp, outp = Net('INPUT'), Net('OUTPUT')
ntwk_ce = vcc & r1 & outp & q1['C,E'] & gnd  # Connect net outp to the junction of the resistor and transistor collector.
ntwk_b = inp & r2 & q1['B']  # Connect net inp to the resistor driving the transistor base.

After that’s done, the inp and outp nets can be connected to other points in the circuit.

Not all networks are composed of parts in series or parallel, for example the Pi matching network. This can be described using the tee() function like so:

inp, outp, gnd = Net('INPUT'), Net('OUTPUT'), Net('GND')
l = Part('Device', 'L')
cs, cl = Part('Device', 'C', dest=TEMPLATE) * 2
pi_ntwk = inp & tee(cs & gnd) & l & tee(cl & gnd) & outp

The tee function takes any network as its argument and returns the first node of that network to be connected into the higher-level network. The network passed to tee can be arbitrarily complex, including any combination of parts, &’s, |’s, and tee’s.

Aliases#

Aliases let you assign a more descriptive name to a part, pin, net, or bus without affecting the original name. This is most useful in assigning names to pins to describe their functions.

r = Part('Device', 'R')
r[1] += vcc  # Connect one end of resistor to VCC net.
r[2].aliases += 'pullup'  # Add the alias 'pullup' to the other end of the resistor.

uc['RESET'] += r['pullup']  # Connect the pullup pin to the reset pin of a microcontroller.

To see the assigned aliases, just use the aliases attribute:

>>> r = Part('Device', 'R')
>>> r[2].aliases += 'pullup'
>>> r[2].aliases += 'aklgjh'  # Some nonsense alias.
>>> r[2].aliases

{'aklghj', 'pullup'}

Units Within Parts#

Some components are comprised of smaller operational units. For example, an operational amplifier chip might contain two individual opamp units, each capable of operating on their own set of inputs and outputs.

Library parts may already have predefined units, but you can add them to any part. For example, a four-pin resistor network might contain two resistors: one attached between pins 1 and 4, and the other bewtween pins 2 and 3. Each resistor could be assigned to a unit as follows:

>>> rn = Part("Device", 'R_Pack02')
>>> rn.make_unit('A', 1, 4)  # Make a unit called 'A' for the first resistor.

 R_Pack02 (): 2 Resistor network, parallel topology, DIP package
    Pin RN1/4/R1.2/PASSIVE
    Pin RN1/1/R1.1/PASSIVE

>>> rn.make_unit('B', 2, 3)  # Now make a unit called 'B' for the second resistor.

 R_Pack02 (): 2 Resistor network, parallel topology, DIP package
    Pin RN1/2/R2.1/PASSIVE
    Pin RN1/3/R2.2/PASSIVE

Once the units are defined, you can use them just like any part:

>>> rn.unit['A'][1,4] += Net(), Net()  # Connect resistor A to two nets.
>>> rn.unit['B'][2,3] += rn.unit['A'][1,4]  # Connect resistor B in parallel with resistor A.

Now this isn’t all that useful because you still have to remember which pins are assigned to each unit, and if you wanted to swap the resistors you would have to change the unit names and the pins numbers!. In order to get around this inconvenience, you could assign aliases to each pin like this:

>>> rn[1].aliases += 'L' # Alias 'L' of pin 1 on left-side of package.
>>> rn[4].aliases += 'R' # Alias 'R' of pin 4 on right-side of package.
>>> rn[2].aliases += 'L' # Alias 'L' of pin 2 on left-side.
>>> rn[3].aliases += 'R' # Alias 'R' of pin 3 on right-side.

Now the same connections can be made using the pin aliases:

>>> rn.unit['A']['L,R'] += Net(), Net()  # Connect resistor A to two nets.
>>> rn.unit['B']['L,R'] += rn.unit['A']['L,R']  # Connect resistor B in parallel with resistor A.

In this case, if you wanted to swap the A and B resistors, you only need to change their unit labels. The pin aliases don’t need to be altered.

If you find the unit[…] notation cumbersome, units can also be accessed by using their names as attributes:

>>> rn.A['L,R'] += Net(), Net()  # Connect resistor A to two nets.
>>> rn.B['L,R'] += rn.A['L,R']   # Connect resistor B in parallel with resistor A.

Part Fields#

Parts typically have fields that store additional information such as manufacturer identifiers. Every Part object stores this information in a dictionary called fields:

>> lm35 = Part('Sensor_Temperature', 'LM35-D')
>> lm35.fields

{'F0': 'U',
 'F1': 'LM35-D',
 'F2': 'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm',
 'F3': ''}

>>> lm35.fields['F1']

'LM35-D'

Key/value pairs stored in fields will get exported in the netlist file when it is generated, so this is the way to pass data to downstream tools like PCBNEW.

New fields can be added just by adding new keys and values to the fields dictionary. Once a field has been added to the dictionary, it can also be accessed and changed as a part attribute:

>>> lm35.fields['new_field'] = 'new value'
>>> lm35.new_field

'new value'

>>> lm35.new_field = 'another new value'
>>> lm35.new_field

'another new value'

Hierarchy#

SKiDL supports two equivalent implementations of hierarchy: subcircuits and packages.

Subcircuits#

SKiDL supports the encapsulation of parts, nets and buses into modules that can be replicated to reduce design effort, and can be used in other modules to create a functional hierarchy. It does this using Python’s built-in machinery for defining and calling functions so there’s almost nothing new to learn.

As an example, here’s the voltage divider as a module:

from skidl import *
import sys

# Define a global resistor template.
r = Part('Device', 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', dest=TEMPLATE)

# Define the voltage divider module. The @subcircuit decorator 
# handles some SKiDL housekeeping that needs to be done.
@subcircuit
def vdiv(inp, outp):
    """Divide inp voltage by 3 and place it on outp net."""
    inp & r(value='1K') & outp & r(value='500') & gnd

# Declare the input, output and ground nets.
input_net, output_net, gnd = Net('IN'), Net('OUT'), Net('GND')

# Instantiate the voltage divider and connect it to the input & output nets.
vdiv(input_net, output_net)

generate_netlist(file_=sys.stdout)

For the most part, vdiv is just a standard Python function: it accepts inputs, it performs operations on them, and it could return results (but in this case, it doesn’t need to). Other than the @subcircuit decorator that appears before the function definition, vdiv is just a Python function and it can do anything that a Python function can do.

Here’s the netlist that’s generated:

(export (version D)
  (design
    (source "C:\TEMP\skidl tests\hier_example.py")
    (date "04/20/2017 09:39 AM")
    (tool "SKiDL (0.0.12)"))
  (components
    (comp (ref R1)
      (value 1K)
      (footprint Resistor_SMD.pretty:R_0805_2012Metric)
      (fields
        (field (name keywords) "r res resistor")
        (field (name description) Resistor))
      (libsource (lib device) (part R)))
    (comp (ref R2)
      (value 500)
      (footprint Resistor_SMD.pretty:R_0805_2012Metric)
      (fields
        (field (name keywords) "r res resistor")
        (field (name description) Resistor))
      (libsource (lib device) (part R))))
  (nets
    (net (code 0) (name GND)
      (node (ref R2) (pin 2)))
    (net (code 1) (name IN)
      (node (ref R1) (pin 1)))
    (net (code 2) (name OUT)
      (node (ref R1) (pin 2))
      (node (ref R2) (pin 1))))
)

For an example of a multi-level hierarchy, the multi_vdiv module shown below can use the vdiv module to divide a voltage multiple times:

from skidl import *
import sys

r = Part('Device', 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', dest=TEMPLATE)

@subcircuit
def vdiv(inp, outp):
    inp & r(value='1K') & outp & r(value='500') & gnd

input_net, output_net, gnd = Net('IN'), Net('OUT'), Net('GND')

@subcircuit
def multi_vdiv(repeat, inp, outp):
    """Divide inp voltage by (3 * repeat) and place it on outp net."""
    for _ in range(repeat):
        out_net = Net()     # Create an output net for the current stage.
        vdiv(inp, out_net)  # Instantiate a divider stage.
        inp = out_net       # The output net becomes the input net for the next stage.
    outp += out_net         # Connect the output from the last stage to the module output net.


input_net, output_net, gnd = Net('IN'), Net('OUT'), Net('GND')

multi_vdiv(3, input_net, output_net)  # Run the input through 3 voltage dividers.

generate_netlist(file_=sys.stdout)

(For the EE’s out there: yes, I know cascading three simple voltage dividers will not multiplicatively scale the input voltage because of the input and output impedances of each stage! It’s just the simplest example I could use to show hierarchy.)

Subcircuits can also be configurable (after all, they’re just functions). The ratio of the voltage divider could be set with a parameter:

# Pass the division ratio as a parameter.
@subcircuit
def vdiv(inp, outp, ratio):
    inp & r(value=1000) & outp & r(value=1000*ratio/(1-ratio)) & gnd

...

# Instantiate the voltage divider with a ratio of 1/3.
vdiv(inp, outp, ratio=0.33)

Packages#

The @subcircuit decorator lets you create a hierarchical circuit where the subcircuits are instantiated using function calls with arguments. The @package decorator is an alternative that packages a subcircuit into a part-like object with its own input and output pins that can be connected to other components. In essence, you’ve encapsulated a subcircuit into its own package with I/O pins.

from skidl import *
import sys

r = Part('Device', 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', dest=TEMPLATE)

# Define the voltage divider module. The @package decorator 
# creates an interface that acts like I/O pins.
@package
def vdiv(inp, outp):
    inp & r(value='1K') & outp & r(value='500') & gnd

input_net, output_net, gnd = Net('IN'), Net('OUT'), Net('GND')

# Instantiate the voltage divider as a package.
divider = vdiv()

# Now connect the I/O pins of the instantiated package to the input & output nets.
divider.inp += input_net
divider.outp += output_net

generate_netlist(file_=sys.stdout)

Subcircuits defined with @package are also customizable via parameters:

from skidl import *
import sys

r = Part('Device', 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', dest=TEMPLATE)

# Voltage divider with a parameterized division ratio.
@package
def vdiv(inp, outp, ratio):
    inp & r(value=1000) & outp & r(value=1000*ratio/(1-ratio)) & gnd

input_net, output_net, gnd = Net('IN'), Net('OUT'), Net('GND')

# Instantiate the voltage divider with a ratio of 1/3.
divider = vdiv(ratio=1.0/3)

divider.inp += input_net
divider.outp += output_net

# You can also override the division ratio. Note that a standard
# assignment operator is used instead of += because ratio is not an I/O pin.
divider.ratio = 0.5

generate_netlist(file_=sys.stdout)

Interfaces#

Passing nets between hierarchically-organized modules can lead to long lists of arguments. To make the code easier to write and understand, SKiDL supports interfaces which are simply dictionaries that encapsulate a number of Bus, Net, or Pin objects. For example, here is an interface for a memory:

mem_intfc = Interface(
  rd = Net('MEM_RD#'),
  wr = Net('MEM_WR#'),
  addr = Bus('MEM_ADDR', 20),
  data = Bus('MEM_DATA', 16)
)

Then this interface can be passed to a module that implements a RAM memory and a microcontroller that uses it:

mem_module(mem_intfc)
uc_module(clk, mem_intfc, io_intfc)

Inside the mem_module, the interface signals are connected to a RAM chip:

@subcircuit
def mem_module(intfc):
  ram = Part('Memory_RAM', 'AS6C1616')
  ram['A[0:19]'] += intfc.addr
  ram['DQ[0:15]'] += intfc.data
  ram['WE#'] += intfc.wr
  ram['OE#'] += intfc['rd']  # Interface members are also accessible using []'s.

Libraries#

As you’ve already seen, SKiDL gets its parts from part libraries. By default, SKiDL finds the libraries provided by KiCad (using the KICAD_SYMBOL_DIR environment variable), so if that’s all you need then you’re all set.

Currently, SKiDL supports the library formats for the following ECAD tools:

KICAD: KiCad schematic part libraries.
SKIDL: Schematic parts stored as SKiDL/Python modules.

You can set the default library format you want to use in your SKiDL script like so:

set_default_tool(KICAD)  # KiCad is the default library format.
set_default_tool(SKIDL)  # Now SKiDL is the default library format.

You can select the directories where SKiDL looks for parts or footprints using the lib_search_paths or footprint_search_paths dictionaries, respectively:

lib_search_paths[SKIDL] = ['.', '..', 'C:\\temp']
lib_search_paths[KICAD].append('C:\\my\\kicad\\libs')

You can convert a KiCad library into the SKiDL format by exporting it:

kicad_lib = SchLib("Device", tool=KICAD)       # Open a KiCad library.
kicad_lib.export('my_skidl_lib')               # Export it into a file in SKiDL format.
skidl_lib = SchLib('my_skidl_lib', tool=SKIDL) # Create a SKiDL library object from the new file.
if len(skidl_lib) == len(kicad_lib):
    print('As expected, both libraries have the same number of parts!')
else:
    print('Something went wrong!')
diode = Part(skidl_lib, 'D')                   # Instantiate a diode from the SKiDL library.

You can make ad-hoc libraries just by creating a SchLib object and adding Part objects to it:

my_lib = SchLib(name='my_lib')                      # Create an empty library object.
my_part = Part(name='R', tool=SKIDL, dest=TEMPLATE) # Create an empty part object template.
my_part.ref_prefix = 'R'                            # Set the part reference prefix.
my_part.description = 'resistor'                    # Set the part's description field.
my_part.keywords = 'res resistor'                   # Set the part's keywords.
my_part += Pin(num=1, func=Pin.PASSIVE)             # Add a pin to the part.
my_part += Pin(num=2, func=Pin.PASSIVE)             # Add another pin to the part.
my_lib += my_part                                   # Add the part to the library.

new_resistor = Part(my_lib, 'R')                    # Instantiate the part from the library.
my_lib.export('my_lib')                             # Save the library in a file my_lib.py.

Always create a part intended for a library as a template so you don’t inadvertently add it to the circuit netlist. Then set the part attributes and create and add pins to the part. Here are the most common attributes you’ll want to set:

Attribute	Meaning
name	A string containing the name of the part, e.g. ‘LM35’ for a temperature sensor.
ref_prefix	A string containing the prefix for this part’s references, e.g. ‘U’ for ICs.
description	A string describing the part, e.g. ‘temperature sensor’.
keywords	A string containing keywords about the part, e.g. ‘sensor temperature IC’.

When creating a pin, these are the attributes you’ll want to set:

Attribute	Meaning
num	A string or integer containing the pin number, e.g. 5 or ‘A13’.
name	A string containing the name of the pin, e.g. ‘CS’.
func	An identifier for the function of the pin.

The pin function identifiers are as follows:

Identifier	Pin Function
Pin.INPUT	Input pin.
Pin.OUTPUT	Output pin.
Pin.BIDIR	Bidirectional in/out pin.
Pin.TRISTATE	Output pin that goes into a high-impedance state when disabled.
Pin.PASSIVE	Pin on a passive component (like a resistor).
Pin.UNSPEC	Pin with an unspecified function.
Pin.PWRIN	Power input pin (either voltage supply or ground).
Pin.PWROUT	Power output pin (like the output of a voltage regulator).
Pin.OPENCOLL	Open-collector pin (pulls to ground but not to positive rail).
Pin.OPENEMIT	Open-emitter pin (pulls to positive rail but not to ground).
Pin.NOCONNECT	A pin that should be left unconnected.

SKiDL will also create a library of all the parts used in your design whenever you use the generate_netlist() function. For example, if your SKiDL script is named my_design.py, then the parts instantiated in that script will be stored as a SKiDL library in the file my_design_lib.py. This can be useful if you’re sending the design to someone who may not have all the libraries you do. Just send them my_design.py and my_design_lib.py and any parts not found when they run the script will be fetched from the backup parts in the library.

No Connects#

Sometimes you will use a part, but you won’t use every pin. The ERC will complain about those unconnected pins:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') 
>>> ERC()
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 1/GP0 of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 3/GP1 of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 4/GP2 of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 5/VDD of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: INPUT pin 6/GP3 of PIC10F220-IOT/U1.

6 warnings found during ERC.
0 errors found during ERC.

If you have pins that you intentionally want to leave unconnected, then attach them to the special-purpose NC (no-connect) net and the warnings will be supressed:

>>> pic10[1,3,4] += NC
>>> ERC()
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 5/VDD of PIC10F220-IOT/U1.
ERC WARNING: Unconnected pin: INPUT pin 6/GP3 of PIC10F220-IOT/U1.

3 warnings found during ERC.
0 errors found during ERC.

In fact, if you have a part with many pins that are not going to be used, you can start off by attaching all the pins to the NC net. After that, you can attach the pins you’re using to normal nets and they will be removed from the NC net:

my_part[:] += NC  # Connect every pin to NC net.
...
my_part[5] += Net()  # Pin 5 is no longer unconnected.

The NC net is the only net for which this happens. For all other nets, connecting two or more nets to the same pin merges those nets and all the pins on them together.

Net and Pin Drive Levels#

Certain parts have power pins that are required to be driven by a power supply net or else ERC warnings ensue. This condition is usually satisfied if the power pins are driven by the output of another part like a voltage regulator. But if the regulator output passes through something like a ferrite bead (to remove noise), then the filtered signal is no longer a supply net and an ERC warning is issued.

In order to satisfy the ERC, the drive strength of a net can be set manually using its drive attribute. As a simple example, consider connecting a net to the power supply input of a processor and then running the ERC:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot') 
>>> a = Net()
>>> pic10['VDD'] += a
>>> ERC()
...
ERC WARNING: Insufficient drive current on net N$1 for pin POWER-IN pin 5/VDD of PIC10F220-IOT/U1
...

To fix this issue, change the drive attribute of the net:

>>> pic10 = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> a = Net()
>>> pic10['VDD'] += a
>>> a.drive = POWER
>>> ERC()
...
(Insufficient drive warning is no longer present.)
...

You can set the drive attribute at any time to any defined level, but POWER is probably the only setting you’ll use. For any net you create that supplies power to devices in your circuit, you should probably set its drive attribute to POWER. This is equivalent to attaching power flags to nets in some ECAD packages like KiCad.

You can also set the drive attribute of part pins to override their default drive level. This can be useful when you are using an output pin of a part to power another part.

>>> pic10_a = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> pic10_b = Part('MCU_Microchip_PIC10', 'pic10f220-iot')
>>> pic10_b['VDD'] += pic10_a[1]  # Power pic10_b from output pin of pic10_a.
>>> ERC()
ERC WARNING: Insufficient drive current on net N$1 for pin POWER-IN pin 5/VDD of PIC10F220-IOT/U2
... (additional unconnected pin warnings) ...

>>> pic10_a[1].drive = POWER  # Change drive level of pic10_a output pin.
>>> ERC()
... (Insufficient drive warning is gone.) ...

Pin, Net, Bus Equivalencies#

Pins, nets, and buses can all be connected to one another in a number of ways. In order to make them as interchangeable as possible, some additional functions are defined for each object:

bool and nonzero: Each object will return True when used in a boolean operation. This can be useful when trying to select an active connection from a set of candidates using the or operator:

>>> a = Net('A')
>>> b = Bus('B', 8)
>>> c = Pin()
>>> d = a or b or c
>>> d
A:
>>> type(d)
<class 'skidl.Net.Net'>

Indexing:Normally, indices can only be used with a Bus object to select one or more bus lines. But Pin and Net objects can also be indexed as long as the index evaluates to zero:

>>> a = Net('A')
>>> c = Pin()
>>> a[0] += c[0]
WARNING: Attaching non-part Pin  to a Net A.
>>> a[0] += c[1]
ERROR: Can't use a non-zero index for a pin.
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "C:\devbisme\KiCad\tools\skidl\skidl\Pin.py", line 251, in __getitem__
    raise Exception
Exception

Iterators: In addition to supporting indexing, Pin, Net and Bus objects can be used as iterators.

>>> bus = Bus('bus', 4)
>>> for line in bus:
    ...:     print(line)
    ...:
bus0:
bus1:
bus2:
bus3:

Width: Bus, Net, and Pin objects all support the width property. For a Bus object, width returns the number of bus lines it contains. For a Net or Pin object, width always returns 1.

>>> a = Net('A')
>>> b = Bus('B', 8)
>>> c = Pin()
>>> a.width
1
>>> b.width
8
>>> c.width
1

Selectively Supressing ERC Messages#

Sometimes a portion of your circuit throws a lot of ERC warnings or errors even though you know it’s correct. SKiDL provides flags that allow you to turn off the ERC for selected nets, pins, and parts like so:

my_net.do_erc = False      # Turns of ERC for this particular net.
my_part[5].do_erc = False  # Turns off ERC for this pin of this part.
my_part.do_erc = False     # Turns off ERC for all the pins of this part.

Customizable ERC Using erc_assert()#

SKiDL’s default ERC will find commonplace design errors, but sometimes you’ll have special requirements. The erc_assert function is used to check these.

from skidl import *
import sys

# Function to check the number of inputs on a net.
def get_fanout(net):
    fanout = 0
    for pin in net.get_pins():
        if pin.func in (Pin.INPUT, Pin.BIDIR):
            fanout += 1
    return fanout

net1, net2 = Net('IN1'), Net('IN2')

# Place some assertions on the fanout of each net.
# Note that the assertions are passed as strings.
erc_assert('get_fanout(net1) < 5', 'failed on net1')
erc_assert('get_fanout(net2) < 5', 'failed on net2')

# Attach some pins to the nets.
net1 += Pin(func=Pin.OUTPUT)
net2 += Pin(func=Pin.OUTPUT)
net1 += Pin(func=Pin.INPUT) * 4  # This net passes the assertion.
net2 += Pin(func=Pin.INPUT) * 5  # This net fails because of too much fanout.

# When the ERC runs, it will also run any erc_assert statements.
ERC()

When you run this code, the ERC will output the following:

ERC ERROR: get_fanout(input_net2) < 5 failed on net2 in <ipython-input-114-5b71f80eb001>:16:<module>.

0 warnings found during ERC.
1 errors found during ERC.

You might ask: “Why not just use the standard Python assert statement?” The reason is that an assert statement is evaluated as soon as it is encountered and would give incorrect results if the nets or other circuit objects are not yet completely defined. But the statement passed to the erc_assert function isn’t evaluated until all the various parts have been connected and ERC() is called (that’s why the statement is passed as a string). Note in the code above that when the erc_assert function is called, no pins are even attached to the net1 or net2 nets, yet. The erc_assert function just places the statements to be checked into a queue that gets evaluated when ERC() is run.

Tags#

If you don’t assign part references (e.g., R1), SKiDL will do it automatically. This saves effort on your part, but if you insert a new part into an existing design, all the part references probably will change during the automatic renumbering. If you already have a PCB layout that associates the footprints to the parts in the netlist using the old references, then the PCB wiring may no longer be consistent with the netlist.

To avoid this problem, tags can be assigned to parts and subcircuits:

def vdiv(inp, outp):
    """Divide inp voltage by 3 and place it on outp net."""
    # Assign a different tag to each resistor.
    inp & r(value='1K', tag=1) & outp & r(value='500', tag=2) & gnd

vdiv(in1, out1, tag='1')  # Create voltage divider with tag '1'.
vdiv(in2, out2, tag='2')  # Create another with tag '2'.

Using tags (which can be any printable object such as a string or number), the timestamps for the resistors in the two voltage dividers will be the same no matter the order in which the subcircuits or the internal resistors are instantiated even though the automatically-assigned references of the resistors will change. The resulting netlist can be imported into layout editors like KiCad’s PCBNEW using the timestamps (instead of part references) and will remain consistent with the PCB wiring traces.

SKIDL Guide

Going Deeper

Contents

Going Deeper#

Basic SKiDL Objects#

Creating SKiDL Objects#

Finding SKiDL Objects#

Copying SKiDL Objects#

Accessing Part Pins#

Accessing Bus Lines#

Making Connections#

Making Serial, Parallel, and Tee Networks#

Aliases#

Units Within Parts#

Part Fields#

Hierarchy#

Subcircuits#

Packages#

Interfaces#

Libraries#

No Connects#

Net and Pin Drive Levels#

Pin, Net, Bus Equivalencies#

Selectively Supressing ERC Messages#

Customizable ERC Using erc_assert()#

Tags#